In high resolution digital-to-analog converters (DACs), performance metrics such as linearity and noise are nominally determined by the matching of parameters derived from physical quantities in the construction of the DACs on an integrated circuit (IC), such as width, length, thickness, doping, etc. As a general rule, for each additional bit of performance in the DAC, parameter matching needs to be twice as tight. This translates to an increase by a factor of four in the IC area required by the DAC. When the DAC resolution is in the 16-bit range, it is no longer practical/economical to use size alone to achieve the required matching.
Over-sampled (sigma-delta) DACs (also referred to as xe2x80x9cconvertersxe2x80x9d) alleviate the need for raw matching using single-bit conversion (so called 1-bit DACs in CD players). A single-bit DAC has only two points in a transfer function of the DAC, and thus is inherently linear. The function of a sigma-delta modulator with a one-bit quantizer is to approximate a high resolution low frequency signal with a high frequency two-level signal. The drawback here is this produces large amounts of out-of-band, for example, high frequency, noise.
One solution is to use more than two levels of quantization. For example, 17 levels may be used. However, now the linearity requirements apply to the fall resolution of the DAC. That is, for a 16-bit DAC, the transfer function of the DAC with these quantization levels must be collinear to 1 part in 216, which is 1 part in 65,536. Such linearity is difficult to achieve with raw parameter matching of the single-bit DACs. Thus, there is need to achieve such linearity in a multi-level DAC using an alternative to raw parameter matching.
Multi-bit DACs have the advantage of significantly increasing the precision limit of the single-bit converter. The major drawback of the multi-bit DAC is the non-linearity presented by the imperfect analog circuit mismatches. Specifically, the non-linearity stems from the mismatching between the unit DAC elements, and causes significant performance degradation. Since the multi-bit DAC is outside the xcex94-xcexa3 modulator, its error cannot be eliminated by the noise-shaping loop of the xcex94-xcexa3 modulator, while the quantization noise inside the xcex94-xcexa3 modulator can be noise-shaped by the xcex94-xcexa3 modulator feedback loop.
There has been a lot of literatures discussing about ways to noise-shape the mismatching error. See,. e.g., I. Galton, xe2x80x9cSpectral Shaping of Circuit Errors in Digital-to-Analog Convertersxe2x80x9d, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, pp. 808-817, vol. 44, no. 10, October 1997; J. Grilo et al., xe2x80x9cA 12-mW ADC Delta-Sigma Modulator with 80dB of Dynamic Range Integrated in a Single-Chip Bluetooth Transceiverxe2x80x9d, IEEE Journal of Solid-State Circuits, pp. 271-278, vol. 37, March 2002; J. Welz, I. Galton, and E. Fogleman, xe2x80x9cSimplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Convertersxe2x80x9d, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, pp, 1014-1027, vol. 48, no. 11, November 2001; R. Adams et al., xe2x80x9cA 113-dB SNR Oversampling DAC with Segmented Noise-Shaped Scramblingxe2x80x9d, IEEE Journal of Solid-State Circuits, pp. 1871-1878, vol. 33, no. 12, December 1998; T. Kwan et al., xe2x80x9cA Stereo Multibit xcexa3xcex94 DAC with Asynchronous Master-Clock Interfacexe2x80x9d, IEEE Journal of Solid-State Circuits, pp. 1881-1887, vol. 31, no. 12, December 1996; A. Yasuda et al., xe2x80x9cA Third-Order xcex94-xcexa3 Modulator Using Second-Order Noise-Shaping Dynamic Element Matchingxe2x80x9d, IEEE Journal of Solid-State Circuits, pp. 1879-1886, vol. 33, no. 12, December 1998; R. Radke et al., xe2x80x9cA Spurious-Free Delta-Sigma DAC Using Rotated Data Weighted Averagingxe2x80x9d, IEEE Custom Integrated Circuits Conference, 1999, pp.125-128; R. Radke and T. S. Fiez, xe2x80x9cImproved xcexa3xcex94 DAC linearity using data weighted averagingxe2x80x9d, IEEE International Symposium, vol.1, pp. 13-16, 1995; R. Radke et al., xe2x80x9cA 14-bit Current-Mode xcexa3xcex94 DAC Based Upon Rotated Data Weighted Averagingxe2x80x9d, IEEE Journal of Solid-State Circuits, vol. 35, no. 8, August 2000. The tree-structure (see I. Galton; J. Grilo et al.; and J. Welz et al., cited above) is one of the best noise-shaping structure, in which the input thermometer code is split into two numbers, which then into four numbers, and so on. The swapping cells is controlled by the Parity Detector outputs, and internally performing arithmetic operations to switch the inputs. The tree-structure results in controlled spectral shaping of the DAC mismatch errors. However, some residual non-linearity due to the DEM remains.
The present invention is directed to a hardware-efficient implementation of dynamic element matching in sigma-delta DAC""s, that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided a data shuffler apparatus for shuffling input bits including a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0xe2x80x2, x1} such that
At least two 4-bit vector shufflers input the vectors {x0xe2x80x2, x1xe2x80x2} and output 4-bit vectors each corresponding to a combination of two vectors {x0xe2x80x2, x1xe2x80x2}, such that the 4-bit vector shufflers operate on the vectors {x0xe2x80x2, x1xe2x80x2} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
In another aspect there is provided a data shuffler apparatus for shuffling input bits including a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0xe2x80x2, x1xe2x80x2} such that a number of 1""s at bit x0xe2x80x2 over time is within xc2x11 of a number of 1""s at bit x1xe2x80x2. At least two 4-bit vector shufflers input the vectors {x0, x1}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0xe2x80x2, x1xe2x80x2} produced by the bit shufflers, such that the 4bit vector shufflers operate on the vectors {x0xe2x80x2, x1xe2x80x2} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
In another aspect there is provided a digital to analog converter including an interpolation filter receiving an N-bit digital input. A delta-sigma modulator receiving an output of the interpolation filter. A dynamic element matching encoder receives N bits from the delta-sigma modulator, and outputs an analog signal corresponding the digital input. The dynamic element matching encoder includes a plurality of bit shufflers each inputting two bits x0 and x1 of the N bits, and outputting a vector {x0xe2x80x2, x1xe2x80x2} such that a number of 1""s at bit x0xe2x80x2 over time is within xc2x11 of a number of 1""s at bit x1xe2x80x2. A plurality of vector shufflers arranged both in parallel and in successive levels input the vectors {x0, x1xe2x80x2} and output vectors each corresponding to a combination of vectors produced by a previous set of shufflers. The vector shufflers operate on their respective input vectors in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the last level of the vector shufflers.
In another aspect there is provided a method of shuffling a plurality of input bits including converting each set of bits x0 and x1 into a vector {x0xe2x80x2, x1xe2x80x2} such that
, inputting the vectors {x0xe2x80x2, x1xe2x80x2} and outputting 4-bit vectors each corresponding to a shuffled combination of two vectors {x0xe2x80x2, x1xe2x80x2}, in the same manner as the bits x0 and x1 are shuffled, updating the current state and for shuffling the bits x0 and x1 based on a next state corresponding to the 4-bit vectors; and continuously repeating the previous steps.
In another aspect there is provided a method of converting a digital signal to an analog signal including filtering the digital signal with an interpolation filter, modulating an output of the interpolation filter with a delta-sigma modulator to produce an N bit signal, receiving the N bits from the delta-sigma modulator, shuffling each set of bits x0 and x1 of the N bits and outputting a vector {x0xe2x80x2, x1xe2x80x2} such that a number of 1""s at x0xe2x80x2 over time is within xc2x11 of a number of 1""s at bit x1xe2x80x2, converting the vectors {x0xe2x80x2, x1xe2x80x2} into 4-bit vectors each corresponding to a combination of two vectors {x0xe2x80x2, x1xe2x80x2}, such that the 4-bit vectors are shuffled in the same manner as the bits x0 and x1, updating a current state and for shuffling the bits x0 and x1 based on a next state used for shuffling the 4-bit vectors, and outputting an analog signal corresponding to the digital signal.
Additional features and advantages of the invention will be set forth in the description that follows. Yet further features and advantages will be apparent to a person skilled in the art based on the description set forth herein or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.